Lead Design Verification Engineer

This Silicon Valley semiconductor leader is seeking a Lead Design Verification Engineer to define, deploy, and grow the expertise of the entire design organization on UVM based verification methodologies and best practices of complex smart connectivity/IoT SoCs.

 Responsibilities:

  • Establish testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
  • Work closely with the design, architecture, and marketing team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology.
  • Develop testbench, test cases, reference model, coverage model and automation of regression suite.
  • Run RTL and gate level functional verification, debug failures, manage bug tracking, and analyze and close coverage.
  • Support mixed-signal co-simulation using Verilog models of analog IP.

Requirements:

  • MS or Ph.D. in Electrical Engineering
  • 5+ years specific experience in verification of complex SOC (Digital/Analog) with high Embedded Software (video/audio) content.
  • Advanced knowledge of standard SoC/ASIC design and verification flows including RTL design, simulation and testbench development.
  • Expertise in HVL and HDL (SystemVerilog, Verilog).
  • Solid verification skills in problem solving, constrained random and direct testing, and debugging.
  • Advanced knowledge of HVL methodology (UVM/OVM).
  • Demonstrated experience developing scripts (Perl/Tcl or Python) for verification flow automation.
  • Solid understanding of complete SoC design flow and verification techniques and methods.

If interested, please email a copy of your resume to jobs@creativehwstaffing.com