Lead Design Verification Engineer
This Silicon Valley semiconductor leader is seeking a Lead Design Verification Engineer to define, deploy, and grow the expertise of the entire design organization on UVM based verification methodologies and best practices of complex smart connectivity/IoT SoCs.
- Establish testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
- Work closely with the design, architecture, and marketing team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology.
- Develop testbench, test cases, reference model, coverage model and automation of regression suite.
- Run RTL and gate level functional verification, debug failures, manage bug tracking, and analyze and close coverage.
- Support mixed-signal co-simulation using Verilog models of analog IP.